1A. Palchaudhuri and A. S. Dhar, "Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability", 28th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Fayetteville, Arkansas, USA, pp. 207. (2020)
2A. Palchaudhuri, S. Sharma and A. S. Dhar, "Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion", 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Seaside, California, USA, pp. 316. (2020)
3A. Palchaudhuri and A. S. Dhar, "FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation", 53rd Annual Asilomar Conference on Signals, Systems, and Computers (ACSSC), Pacific Grove, CA, USA, pp. 1555-1559. (2019)
4 A. Palchaudhuri and A. S. Dhar, "VLSI Architectures for Jacobi Symbol Computation", 32nd International Conference on VLSI Design (VLSID), New Delhi, India, pp. 335-340. (2019)
5A. Palchaudhuri and A. S. Dhar, "Redundant Binary to Two's Complement Converter on FPGAs through Fabric Aware Scan Based Encoding Approach for Fault Localization Support", IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 25th Reconfigurable Architectures Workshop (RAW), Vancouver, British Columbia Canada, pp. 218-221. (2018)
6A. Palchaudhuri and A. S. Dhar, "Fast Carry Chain based Architectures for Two's Complement to CSD Recoding on FPGAs", 14th International Symposium on Applied Reconfigurable Computing (ARC), Santorini, Greece, pp. 537-550. (2018)
7A. Palchaudhuri and A. S. Dhar, "High Speed FPGA Fabric Aware CSD Recoding with Run-time Support for Fault Localization", 31st International Conference on VLSI Design (VLSID), Pune, India, pp. 186-191. (2018)
8A. Palchaudhuri and A. S. Dhar, "Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs", 24th IEEE International Conference on High Performance Computing (HiPC), Jaipur, India, pp. 104-113. (2017)
9A. Palchaudhuri and A. S. Dhar, "Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs", 21st International Symposium on VLSI Design and Test (VDAT), Roorkee, India, pp. 594-606. (2017)
10A. Palchaudhuri and A. S. Dhar, "High Performance Bit-Sliced Pipelined Comparator Tree for FPGAs", 20th International Symposium on VLSI Design and Test (VDAT), Guwahati, India, pp. 1-6. (2016)
11A. Palchaudhuri and A. S. Dhar, "Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs", 29th International Conference on VLSI Design (VLSID), Kolkata, India, pp. 433-438. (2016)
12 A. Palchaudhuri, R. S. Chakraborty and D. P. Sahoo, "Automated Design of High Performance Integer Arithmetic Cores on FPGA", 18th Euromicro Conference on Digital System Design (DSD), Madeira, Portugal, pp. 322-329. (2015)
13A. Palchaudhuri, R. S. Chakraborty, Md. Salman, S. Kardas and D. Mukhopadhyay, "Highly Compact Automated Implementation of Linear CA on FPGAs", Cellular Automata - 11th International Conference on Cellular Automata for Research and Industry (ACRI), Krakow, Poland. Published in Lecture Notes on Computer Science, Springer, vol. 8751, pp. 388-397. (2014)
14S. Burman, A. Palchaudhuri, R. S. Chakraborty, D. Mukhopadhyay and P. Singh, "Effect of Malicious Hardware Logic on Circuit Reliability", 16th International Symposium on VLSI Design and Test (VDAT), Shibpur, India. Published in Lecture Notes on Computer Science, Springer, vol. 7373, pp. 190-197. (2012)