1S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Dasgupta, and A. Bulusu, "A New Insight into the Saturation Phenomenon in Nanosheet Transistor: A Device Optimization Perspective," IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023
2N. Gandhi, R. K. Jaisawal, S. Rathore, P. N. Kondekar, S. Banchhor, and N. Bagga, "Demonstration of a Junctionless Negative Capacitance FinFET-based Hydrogen Gas Sensor: A Reliability Perspective," IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023
3J. Patel, N. Aggarwal, N. Bagga, and S. Dasgupta, "Small-Signal Model of Nanosheet FET for High-Frequency Range: A Design Perspective of Parallel Stacking and Dual-Dielectric Spacer," IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023
4R. K. Jaisawal, S.Rathore, N. Gandhi, P. N. Kondekar, S. Banchhor, V B. Sreenivas, Y. S. Song, and N. Bagga, "Self-Heating and Interface Traps Assisted Early Aging Revelation and Reliability Analysis of Negative Capacitance FinFET, " IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023
5S. Rathore, R. K. Jaisawal, P. N. Kondekar, N. Gandhi, S. Banchhor, Y. S. Song, and N. Bagga, "Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET," IEEE International Reliability Physics Symposium (IRPS), California, USA, March 2023
6S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, "Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET," IEEE ICEE 2022, Bangalore, India. (BEST Paper)
7R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, "Role of Interfacial Oxide on Capacitance Matching in a Negative Capacitance FinFET: A Reliability Perspective," IEEE ICEE 2022, Bangalore, India.
8J. Patel, N. Bagga, S. Banchhor, and S. Dasgupta, "Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation," IEEE ICEE 2022, Bangalore, India.
9M. Subramaniyan, N. Chauhan, N. Bagga, A. Kumar, S. Banchhor, S. Roy, A. Dasgupta, A. Bulusu, and S. Dasgupta, "Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors," IEEE ICEE 2022, Bangalore, India.
10R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, “Reliability of TCAD Study for HfO2-doped Negative Capacitance FinFET with Different Material Specific Dopants, SISPAD’22, Granada Spain, September 2022
11S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, “Trap and Self-Heating Effect Based Reliability Analysis to Reveal Early Aging Effect in Nanosheet FET,” SISPAD’22, Granada Spain, September 2022
12Navjeet Bagga, Kai Ni, Nitanshu Chauhan, Om Prakash, Sharon Hu and Hussam Amrouch, "Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage," In Proceedings of the IEEE 60th International Reliability Physics Symposium (IRPS’22), Dallas, U.S., 2022.
13N. Chauhan, C. Garg, Kai Ni, A. Behera, S. Yadav, S. Banchhor, N. Bagga, A. Dasgupta, A. Datta, S. Dasgupta, A. Bulusu, "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI," In Proceedings of the IEEE 60th International Reliability Physics Symposium (IRPS’22), Dallas, U.S., 2022.
14R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, “Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (alpha),” VDAT’22, Jammu, India, July-2022.
15N. Chauhan, A. Gupta, G. Bajpai, N. Bagga, S. Banchhor, S. Dasgupta and A. Bulusu, “Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective,” VDAT’22, Jammu, India, July-2022.
16S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Roy, A. Bulusu and S. Dasgupta, "Analysis of Self-Heating in 5nm Stacked Nanosheet Transistor Applications, In Proceedings of XXI International Workshop on the Physics of Semiconductor Devices (IWPSD 2021), Dec. 2021.
17V. Chauhan, D. P. Samajdar and N. Bagga, “Performance Investigation of Ferroelectric Spacers for Negative Capacitance FinFETs,” Proc. of Int. Symp. On Materials of the Millennium: Emerging Trends and Future Prospects, 2021.
18N. Jain, I. Mal, D. Samajdar and N. Bagga, “Investigation of Optical and Electronic Properties of InAsNBi for Infrared Detection,” Proc. of Int. Symp. On Materials of the Millennium: Emerging Trends and Future Prospects, 2021.
19A. Dixit, D. P. Samajdar and N. Bagga, “Label-Free Biosensing using Dielectric Modulated GaAs1-xSbx FinFET under Dry/Wet Environment, in Proc. IEEE INDICON, Dec. 2021.
20A. Dixit, D. P. Samajdar and N. Bagga, “GaAs1-xSbx Label-Free Biosensor using Trigate and Gate-all-around FET,” in Proc. IEEE IBSSC, Nov. 2021.
21S. Sarkhel, R. R. Dey, S. Das, S. Sarkar, T. Santra, and N. Bagga, “A Novel Dual Metal Double Gate Grooved Trench MOS Transistor: Proposal and Investigation,” in Proc. Springer COMSYS, Oct. 2021.
22A. Dixit, D. P. Samajdar and N. Bagga, "Performance Evolution of the GaAs1-xSbx FinFET for the Mole Fraction Variation," IEEE DeviC Conference, May 2021.
23A. Gupta, G. Bajpai, P. Singhal, N. Bagga, Om Prakash, S. Banchhor, H. Amrouch, and N. Chauhan, "Traps Based Reliability Barrier on Performance and Revealing Early Ageing in Negative Capacitance (NC) FET," Proc. IEEE IRPS, March 2021.
24A. Dixit, D.P. Samajdar, V. Chauhan and N. Bagga, “Performance Comparison of III-V and Silicon FinFETs for Ultra-Low Power VLSI Applications,” Proc. IEEE CCSN, 2020 (Best Paper)
25S Sarkhel, and N Bagga, "Analytical Model of a Strain Induced Lateral Channel Workfunction Engineered Surrounding Gate MOSFET," Proc. IEEE ASPCON, 2020.
26N. Chauhan, G. Bajpai, S. Banchhor, and N. Bagga, "Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification," 24th International Symposium on VLSI Design and Test (VDAT), Jul. 2020.
27N. Bagga, N. Chauhan, A. Bulusu and S. Dasgupta, “Demonstration of Novel Ferroelectric-Dielectric Tunnel FET, IEEE Proc. of MOS-AK, 2019.
28N. Bagga and S. Dasgupta, “Demonstration of Novel Structures for Improvement in Performance of Tunnel FETs,” Ph.D. Forum at VLSI Design Conference, 2019.
29N. Chauhan, N. Bagga, S. Banchhor, S. Dasgupta and A. Bulusu, “Simulation Study of Transient Negative Capacitance with Stabilization and Amplification,” Proc. IWPSD, 2019.
30D. Gupta, N. Bagga and S. Dasgupta, “Reduced Gate Capacitance of Dual Metal Double Gate over Single Metal Double Gate Tunnel FET: A Comparative Study,” Proc. IEEE ICEDSS, 2018.
31N. Bagga and S. Dasgupta, “Analytical Threshold Voltage Model of Gate All Around Triple Metal Tunnel FET,” Proc. IEEE of ICEDSS, pp. 146-149, Mar. 2017.
32N. Bagga, Anil Kumar and S. Dasgupta, “SOI Based Double Source Tunnel FET (DS-TFET) with High On-Current and Reduced Turn-on Voltage,” Proc. IEEE of MIEL, Serbia, Europe, 2017. (BEST Paper)
33N. Bagga, Saheli Sarkhel and S. K. Sarkar, “Analytical Model for ID-VD characteristics of a Triple Metal Double Gate TFET,” Proc. IEEE ICCCA, 2016.
34N. Bagga, S. Sarkhel and S. K. Sarkar, “Recent Research Trends in Gate Engineered Tunnel FET for Improved Current Behavior by subduing the Ambipolar Effects: A Review,” Proc. IEEE ICCCA, 2015.
35P. K. Dutta, Navjeet Bagga, K. Naskar and S. K. Sarkar, “Analysis and Simulation of Dual Metal Double Gate SON MOSFET using Hafnium Dioxide for Better Performance,” Proc. of IET, 2015.
36Saheli Sarkhel, Navjeet Bagga and S. K. Sarkar, " Analytical Modeling and Simulation of Work function Engineered Gate Junction-less high-k dielectric Double Gate MOSFET: A Comparative Study," Proc. of IET, 2015.
