Dr. Navjeet BaggaAssistant Professor
School of Electrical Sciences

Research Interests

Emerging Nanoscale Devices; Semiconductor Device Modelling; Low power Devices; Reliability Analysis; Ferroelectric-based devices; Device Circuit Co-design; FET-based Biosensors.

Contact Details

  • SES A-104
  • navjeet@iitbbs.ac.in

Other Profile Link(s)

Education

 Degree Discipline Year School
 Ph.D. Microelectronics and VLSI 2019 Indian Institute of Technology Roorkee
 M.E. Electronics and Telecommunication Engineering 2015 Jadavpur University
 B.E. Electronics and Telecommunication Engineering 2012 Government Engineering College Bilaspur
 

Biosketch

 

 

Projects

1. N. Bagga and V. Bajaj, "AI and ML based data analytics algorithm for Medtech System," Consultancy Project, (Completed).
2. N. Bagga, "Design and Performance Investigation of Negative Capacitance Tunnel FET for Digital/Analog Applications," FIG PDPM IIITDMJ. (Completed)
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Recent Publications (International Journals)

1R. K. Jaisawal, S. Rathore, P.N. Kondekar, and N. Bagga, "Reliability of TCAD study for HfO2-doped Negative capacitance FinFET with different Material-Specific dopants," Solid-State Electronics, vol. 199, pp. 108531, Nov. 2022.
2T. Santra, A. Dixit, R. K. Jaisawal, S.Rathore, S. Sarkhel, and N. Bagga, "Investigation of Geometrical Impact on a P+ Buried Negative Capacitance SOI FET," Microelectronics Journal, Oct. 2022.
3S. Rathore, R. K. Jaisawal, N. Gandhi, P.N. Kondekar, and N. Bagga, "Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor," Microelectronics Journal, vol. 129, pp. 105590, Sept. 2022.
4R. K. Jaisawal, S. Rathore, N. Gandhi, P. N. Kondekar, and Navjeet Bagga, "Role of Temperature on Linearity and Analog/RF Performance Merits of a Negative Capacitance FinFET," Semiconductor Science and Technology, vol. 37, pp. 115003, Sept. 2022.
5V. Chauhan, D. P. Samajdar, and N. Bagga, “Exploration and Device Optimization of Dielectric-Ferroelectric Sidewall Spacer in Negative Capacitance FinFET,” IEEE Transaction on Electron Devices, Early Access, July 2022, doi: 10.1109/TED.2022.3186272.
6S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, “Design Optimization of Three-Stacked Nanosheet FET from Self-Heating Effects Perspective, IEEE Transactions on Device and Materials Reliability, Early Access, June 2022, doi: 10.1109/TDMR.2022.3181672.
7 V. Chauhan, D. P. Samajdar, and N. Bagga, “Demonstration of Improved Short Channel Performance Metrics for Ferroelectric Concentric Negative Capacitance FinFET,” Silicon Springer, June 2022, doi: https://doi.org/10.1007/s12633-022-01993-0.
8V. Chauhan, D. P. Samajdar, and N. Bagga, “Quasi-analytical model of surface potential and drain current for Trigate negative capacitance FinFET: a superposition approach,” Semi. Sci. Tech., Jul. 2022.
9R. K. Jaisawal, S. Rathore, P. N Kondekar, S. Yadav, B. Awadhiya, P. Upadhyay and N. Bagga, "Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques," Semiconductor Science and Technology, March. 2022.
10N. Jain, I. Mal, D P Samajdar, and N. Bagga, “Theoretical Exploration of the Optoelectronic Properties of InAsNBi/InAs heterostructures for Infrared Applications: A Multi-Band k.p Approach,” Materials Science in Semiconductor Processing, vol. 148, pp. 106822, April 2022, doi: https://doi.org/10.1016/j.mssp.2022.106822.
11A. Dixit, D. P. Samajdar and N. Bagga, “Demonstration of Geometrical Impact of Nanowire on GaAs1-xSbx Transistor Performance,” IEEE Transaction on Electron Devices, Dec. 2021.
12N. Chauhan, N. Bagga, S. Banchhor, C. Garg, A. Sharma, A. Datta, S. Dasgupta and A. Bulusu, "BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective," Nanotechnology IOP Science, Oct. 2021.
13N. Chauhan, N. Bagga, S. Banchhor, A. Datta, S. Dasgupta, and B. Anand, “Negative to Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits,” IEEE Transactions on Ultrasonic, Ferroelectrics and Frequency control, Sept. 2021
14A. Dixit, D. P. Samajdar and N. Bagga, “Impact of the mole fraction modulation on the RF/DC performance of GaAs1-xSbx FinFET,” Int. Jour. of Numerical Modelling, Electronic Devices and Fields, Sept. 2021.
15V. Chauhan, D. P. Samajdar, N. Bagga and A. Dixit, "A Novel Negative Capacitance FinFET with Ferroelectric Spacer: Proposal and Investigation," IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Early Access, Jul. 2021.
16A.Dixit, D.P.Samajdar, and N. Bagga, "Dielectric Modulated GaAs1-xSbX FinFET as a Label-Free Biosensor: Device Proposal and Investigation," Semiconductor Science and Technology, IOP Science, Early Access, Jun. 2021.
17A. Dixit, D. P. Samajdar, N. Bagga, D. S. Yadav, "Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric," vol. 26, Materials Today Communications, Mar. 2021.
18N. Bagga, N. Chauhan, S. Banchhor, D. Gupta and S. Dasgupta, “Demonstration of a Novel Tunnel FET with Channel Sandwiched by Drain,” Semi. Sci. and Tech. IOP, vol. 35, Nov. 2019.
19N. Bagga, N. Chauhan, D. Gupta and S. Dasgupta, “A Novel Twofold Tunnel FET with Reduced Miller Capacitance: Proposal and Investigation,” IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 3202-3208, Jul. 2019.
20N. Bagga, Anil Kumar and S. Dasgupta, “Demonstration of a Novel Two Source Region Tunnel FET,” IEEE Transactions on Electron Devices, vol. 64, issue 12, pp. 5256-5262, Oct. 2017.
21N. Bagga and S. Dasgupta, “Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET, IEEE Trans. Electron Devices , vol. 64, issue 2, pp. 606 – 613, 2017.
22N. Bagga, Anil Kumar, A. Bhattacharjee and S. Dasgupta, “Performance evaluation of a novel GAA Schottky Junction TFET with heavily doped pocket, Superlattices and Microstructures, 2017.
23S. Sarkhel, N. Bagga and S. K. Sarkar, “A compact analytical model of binary metal alloy silicon-on-nothing (BMASON) tunnel FET with interface trapped charges,” Journal of Computational Electronics, doi: 10.1007/s10825-017-1030-7, pp. 1-10, 2017.
24N. Bagga, Saheli Sarkhel and S. K. Sarkar, “Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance,” IETE Journal of Research, vol. 62, no. 6, pp. 786-794, 2016.
25S. Sarkhel, N. Bagga and S. K. Sarkar, “Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor,” Journal of Computational Electronics, vol. 15, no. 1, pp. 104–114, 2016.
26N. Bagga and S. K. Sarkar, “An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET, IEEE Trans. Electron Devices, vol. 62, no. 7, pp. 2136 – 2142, 2015.

Conferences (International)

1S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, "Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET," IEEE ICEE 2022, Bangalore, India.
2R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, "Role of Interfacial Oxide on Capacitance Matching in a Negative Capacitance FinFET: A Reliability Perspective," IEEE ICEE 2022, Bangalore, India.
3J. Patel, N. Bagga, S. Banchhor, and S. Dasgupta, "Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation," IEEE ICEE 2022, Bangalore, India.
4M. Subramaniyan, N. Chauhan, N. Bagga, A. Kumar, S. Banchhor, S. Roy, A. Dasgupta, A. Bulusu, and S. Dasgupta, "Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors," IEEE ICEE 2022, Bangalore, India.
5R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, “Reliability of TCAD Study for HfO2-doped Negative Capacitance FinFET with Different Material Specific Dopants, SISPAD’22, Granada Spain, September 2022
6S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, “Trap and Self-Heating Effect Based Reliability Analysis to Reveal Early Aging Effect in Nanosheet FET,” SISPAD’22, Granada Spain, September 2022
7Navjeet Bagga, Kai Ni, Nitanshu Chauhan, Om Prakash, Sharon Hu and Hussam Amrouch, "Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage," In Proceedings of the IEEE 60th International Reliability Physics Symposium (IRPS’22), Dallas, U.S., 2022.
8N. Chauhan, C. Garg, Kai Ni, A. Behera, S. Yadav, S. Banchhor, N. Bagga, A. Dasgupta, A. Datta, S. Dasgupta, A. Bulusu, "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI," In Proceedings of the IEEE 60th International Reliability Physics Symposium (IRPS’22), Dallas, U.S., 2022.
9R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, “Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (alpha),” VDAT’22, Jammu, India, July-2022.
10N. Chauhan, A. Gupta, G. Bajpai, N. Bagga, S. Banchhor, S. Dasgupta and A. Bulusu, “Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective,” VDAT’22, Jammu, India, July-2022.
11S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Roy, A. Bulusu and S. Dasgupta, "Analysis of Self-Heating in 5nm Stacked Nanosheet Transistor Applications, In Proceedings of XXI International Workshop on the Physics of Semiconductor Devices (IWPSD 2021), Dec. 2021.
12V. Chauhan, D. P. Samajdar and N. Bagga, “Performance Investigation of Ferroelectric Spacers for Negative Capacitance FinFETs,” Proc. of Int. Symp. On Materials of the Millennium: Emerging Trends and Future Prospects, 2021.
13N. Jain, I. Mal, D. Samajdar and N. Bagga, “Investigation of Optical and Electronic Properties of InAsNBi for Infrared Detection,” Proc. of Int. Symp. On Materials of the Millennium: Emerging Trends and Future Prospects, 2021.
14A. Dixit, D. P. Samajdar and N. Bagga, “Label-Free Biosensing using Dielectric Modulated GaAs1-xSbx FinFET under Dry/Wet Environment, in Proc. IEEE INDICON, Dec. 2021.
15A. Dixit, D. P. Samajdar and N. Bagga, “GaAs1-xSbx Label-Free Biosensor using Trigate and Gate-all-around FET,” in Proc. IEEE IBSSC, Nov. 2021.
16S. Sarkhel, R. R. Dey, S. Das, S. Sarkar, T. Santra, and N. Bagga, “A Novel Dual Metal Double Gate Grooved Trench MOS Transistor: Proposal and Investigation,” in Proc. Springer COMSYS, Oct. 2021.
17A. Dixit, D. P. Samajdar and N. Bagga, "Performance Evolution of the GaAs1-xSbx FinFET for the Mole Fraction Variation," IEEE DeviC Conference, May 2021.
18A. Gupta, G. Bajpai, P. Singhal, N. Bagga, Om Prakash, S. Banchhor, H. Amrouch, and N. Chauhan, "Traps Based Reliability Barrier on Performance and Revealing Early Ageing in Negative Capacitance (NC) FET," Proc. IEEE IRPS, March 2021.
19A. Dixit, D.P. Samajdar, V. Chauhan and N. Bagga, “Performance Comparison of III-V and Silicon FinFETs for Ultra-Low Power VLSI Applications,” Proc. IEEE CCSN, 2020 (Best Paper)
20S Sarkhel, and N Bagga, "Analytical Model of a Strain Induced Lateral Channel Workfunction Engineered Surrounding Gate MOSFET," Proc. IEEE ASPCON, 2020.
21N. Chauhan, G. Bajpai, S. Banchhor, and N. Bagga, "Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification," 24th International Symposium on VLSI Design and Test (VDAT), Jul. 2020.
22N. Bagga, N. Chauhan, A. Bulusu and S. Dasgupta, “Demonstration of Novel Ferroelectric-Dielectric Tunnel FET, IEEE Proc. of MOS-AK, 2019.
23N. Bagga and S. Dasgupta, “Demonstration of Novel Structures for Improvement in Performance of Tunnel FETs,” Ph.D. Forum at VLSI Design Conference, 2019.
24N. Chauhan, N. Bagga, S. Banchhor, S. Dasgupta and A. Bulusu, “Simulation Study of Transient Negative Capacitance with Stabilization and Amplification,” Proc. IWPSD, 2019.
25D. Gupta, N. Bagga and S. Dasgupta, “Reduced Gate Capacitance of Dual Metal Double Gate over Single Metal Double Gate Tunnel FET: A Comparative Study,” Proc. IEEE ICEDSS, 2018.
26N. Bagga and S. Dasgupta, “Analytical Threshold Voltage Model of Gate All Around Triple Metal Tunnel FET,” Proc. IEEE of ICEDSS, pp. 146-149, Mar. 2017.
27N. Bagga, Anil Kumar and S. Dasgupta, “SOI Based Double Source Tunnel FET (DS-TFET) with High On-Current and Reduced Turn-on Voltage,” Proc. IEEE of MIEL, Serbia, Europe, 2017.
28N. Bagga, Saheli Sarkhel and S. K. Sarkar, “Analytical Model for ID-VD characteristics of a Triple Metal Double Gate TFET,” Proc. IEEE ICCCA, 2016.
29N. Bagga, S. Sarkhel and S. K. Sarkar, “Recent Research Trends in Gate Engineered Tunnel FET for Improved Current Behavior by subduing the Ambipolar Effects: A Review,” Proc. IEEE ICCCA, 2015.
30P. K. Dutta, Navjeet Bagga, K. Naskar and S. K. Sarkar, “Analysis and Simulation of Dual Metal Double Gate SON MOSFET using Hafnium Dioxide for Better Performance,” Proc. of IET, 2015.
31Saheli Sarkhel, Navjeet Bagga and S. K. Sarkar, " Analytical Modeling and Simulation of Work function Engineered Gate Junction-less high-k dielectric Double Gate MOSFET: A Comparative Study," Proc. of IET, 2015.

Conferences (National)

1P. K. Dutta, Navjeet Bagga, K. Naskar and S. K. Sarkar, “A comparative analysis of Nano SON DMDG MOSFET using Hafnium oxide as dielectric for better performance,” Proc. IEEE ICCCS, 2015.
 

Academic Honors & Awards

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Professional Experience

1. Assistant Professor at PDPM-Indian Institute of Information Technology Design and Manufacturing Jabalpur (2022).                                2. Post Doc. Fellow at Karlsruhe Institute of Technology Germany, (2020).                                                                                                              3. Research Associate at  Indian Institute of Technology Roorkee, (2019).

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