Dr. Nijwm WaryAssistant Professor
School of Electrical Sciences
(Electronics & Communication Engineering)

Research Interests

Analog CMOS VLSI circuit design; Circuit design for high speed serial link (full-duplex, 4-PAM signaling, CTLE and DFE design, Equalizer adaptation);  Signaling across Silicon interposer and MCM; On-Chip DC-DC converters.

Contact Details

  • SES-008
  • 674 713 5764
  • nijwmwary@iitbbs.ac.in

Other Profile Link(s)

Education

 Degree Discipline Year School
 Ph.D. Microelectronics and VLSI Design 2018 Indian Institute of Technology Kharagpur
 M.Tech Microelectronics and VLSI Design 2012 Indian Institute of Technology Kharagpur
 B.Tech Electronics and Electrical Comm. Eng. 2012 Indian Institute of Technology Kharagpur
 

Biosketch

Nijwm Wary received the B.Tech. and M.Tech. degrees in electronics from the Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology (IIT) Kharagpur, Kharagpur, India, in 2012, and the Ph.D. degree in electronics from IIT Kharagpur in 2018. He was a Postdoctoral Fellow with the Integrated System Lab, University of Toronto, Canada, from 2018 to 2019. Since January 2020, he has been with the School of Electrical Science, IIT Bhubaneswar, India, where he joined as an Assistant Professor. His research interests include CMOS circuit design for high-speed interface for chip-to-chip communication, DC-DC converters and energy harvesting.

Teaching

Low Power VLSI Circuits & Systems; Basic Electronics; Digital Electronics Circuits; Introduction to Signal Processing; Basic Electronics Lab; Digital Electronics Circuits Lab.

Projects

Sponsored Research Projects

1. Title: High-speed and energy efficient CMOS transceiver design for full-duplex chip-to-chip serial link

Funding Agency: DST-SERB

Duration: 2 years

Role: Principal Investigator

 

2. Title: Design and Development of Next Generation Cost Effective Reconfigurable On-Board Battery Charger with Health and Fault Monitoring

Funding Agency: MEITY

Duration: 2 years

 

Role: Co-Principal Investigator
 
 

Industrial Consultancy

Title: Analog Design for Serial Link
Funding Agency: Ceremorphic Inc.
Duration: 4 years
Role: Principal Investigator
 

Recent Publications (International Journals)

1P. Chandrika Kondeti, Suraj Kumar P. and N. Wary,”Current-Integrating Summer for DFE Receiver With Low Common Mode Variation”, Microelectronics Journal, Elsevier, Vol. 123, May 2022
2X. Mo, J. Wu, N. Wary and T. C. Carusone, "Design Methodologies for Low-Jitter CMOS Clock Distribution," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 94-103, 2021.
3B. Vatankhahghadim, N. Wary, J. Bailey and A.Chan Carusone, “A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s”, IEEE Open Journal of Circuits and Systems, vol. 2, pp. 78-90, 2021
4A. R. Chowdhury, N. Wary and P. Mandal, “Hybrid Bidirectional Transceiver for Multipoint-to-Multipoint Signaling Across On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol. 14, Issue 6, pp. 780-787, Sept. 2020
5B. Dehlaghi, N. Wary and A.Chan Carusone, “Ultra-Short-Reach Interconnects for Die-to-Die Links”, IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 42-53, Spring 2019.
6 N. Wary and P. Mandal, “Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects”, IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2026-2037, Aug. 2017.
7N. Wary and P. Mandal, “Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects”, IEEE Transactions on Very Large Scale Integration, vol. 25, no. 9, pp. 2575-2587, Sept. 2017.
8N. Wary and P. Mandal, “High Speed Energy Efficient Bi-directional Transceiver for On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol.9, Issue 5, pp. 319-327, Sept. 2015.
9N. Wary and P. Mandal, “A low impedance receiver for power efficient current mode signalling across on-chip global interconnects”, International Journal Electronic and Communication, Elsevier, Vol. 68, No. 10, pp. 969-975, Oct 2014.

Conferences (International)

1Nishant Maurya and N. Wary, “Design and Analysis of PVT Invariant Current Reference in 65-nm CMOS” 65th IEEE International Midwest Symposium on Circuits and Systems, Fukuoka, Japan, 2022 (accepted).
2Prema Kumar G., N. Wary and Vijaya Sankara Rao P., “Power Efficient Echo-Cancellation Based Hybrid forFull-Duplex Chip-to-Chip Interconnects”, IEEE International Symposium on Circuits & Systems, Texas, Austin, 2022.
3Prema Kumar G., N. Wary and Vijaya Sankara Rao P., “Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects”, IEEE International Symposium on Circuits & Systems, Texas, Austin, 2022. (accepted)
4B. Vatankhahghadim, N. Wary and A.Chan Carusone, “Discrete Multitone Signalling for wireline Communication”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct. 12-14, 2020.
5P. Chen, N. Wary and A.Chan Carusone,”All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct 12-14, 2020.
6A. R. Chowdhury, N. Wary and P. Mandal, “A Regulated-Cascode Based Current-Integrating TIA RX with 1-Tap Speculative Adaptive DFE”, 2019 62nd IEEE International Midwest Symposium on Circuits and Systems, Dallas, TX, USA, 2019, pp. 790-793.
7A. R. Chowdhury, N. Wary and P. Mandal, “Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination”, 2019 32th International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi, Jan 2019, pp.25-30.
8N. Wary and P. Mandal,”Current-Mode Simultaneous Bidirectional Transceiver for On-Chip Global Interconnects”, Quality Electronic Design (ASQED), 2015 6th Asia Symposium on,Kuala Lumpur, Aug. 2015, pp. 19-24.
 

Academic Honors & Awards

  • IIT Bhubaneswar- Teaching Excellence Award, 2022
 

Research Scholar

Ph. D.:
  • Suraj Kumar Prusty 
M.Tech. :
  • Sahil Dalvi
  • Vinay Gavade
  • Sugandha Sharma
  • Poorna Chandrika Kondeti
B.Tech:
  • V K Surya
  • Y Anish Reddy
  • Konangi Revanth
  • Nishant Maurya
  • Ranjan Ashish
  • Sudipta Gyan Prakash Pradhan
  • Sai Madhav A
  • Karnati Abhinay
 

Book Chapter

  • X. Mo, N. Wary, and A. Chan Carusone, “High-Performance CMOS Clock Distribution,”  in Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems, Editor W. Rhee, The Institution of Engineering and Technology, 2020. [Link]

Professional Experience

Postdoctoral Fellow at University of Toronto (June 2018- Dec 2019). Research area: High speed serial link design. Research Group: Integrated System Lab of Prof. Tony Chan Carusone

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