1Suraj Kumar P., V. K. Surya and N. Wary, “Energy Efficient Integrated Summer and Latch Based DFE With Reduced Tap Loading”, IEEE Transactions on Circuits and Systems II, 2023. (accepted for publication)
2S. K. Prusty, S. P. Dash, V. K. Surya, and N. Wary, “Differential evolution based adaptation algorithm for multi-stage continuous time linear equalizer,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 12, pp. 2046-2049, Dec. 2023.
3P. Chandrika Kondeti, Suraj Kumar P. and N. Wary, ''Current-Integrating Summer for DFE Receiver With Low Common Mode Variation", Microelectronics Journal, Elsevier, Vol. 123, May 2022
4X. Mo, J. Wu, N. Wary and T. C. Carusone, "Design Methodologies for Low-Jitter CMOS Clock Distribution," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 94-103, 2021.
5B. Vatankhahghadim, N. Wary, J. Bailey and A.Chan Carusone, ''A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s", IEEE Open Journal of Circuits and Systems, vol. 2, pp. 78-90, 2021
6A. R. Chowdhury, N. Wary and P. Mandal, “Hybrid Bidirectional Transceiver for Multipoint-to-Multipoint Signaling Across On-Chip Global Interconnectsâ€, IET Circuit, Devices and System, Vol. 14, Issue 6, pp. 780-787, Sept. 2020
7B. Dehlaghi, N. Wary and A.Chan Carusone, “Ultra-Short-Reach Interconnects for Die-to-Die Linksâ€, IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 42-53, Spring 2019.
8 N. Wary and P. Mandal, “Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnectsâ€, IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2026-2037, Aug. 2017.
9N. Wary and P. Mandal, “Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnectsâ€, IEEE Transactions on Very Large Scale Integration, vol. 25, no. 9, pp. 2575-2587, Sept. 2017.
10N. Wary and P. Mandal, “High Speed Energy Efficient Bi-directional Transceiver for On-Chip Global Interconnectsâ€, IET Circuit, Devices and System, Vol.9, Issue 5, pp. 319-327, Sept. 2015.
11N. Wary and P. Mandal, “A low impedance receiver for power efficient current mode signalling across on-chip global interconnectsâ€, International Journal Electronic and Communication, Elsevier, Vol. 68, No. 10, pp. 969-975, Oct 2014.