Dr. Pasupureddi Vijaya Sankara RaoAssociate Professor
School of Electrical Sciences
(Electronics & Communication Engineering)

Research Interests

Analog, RF and Mixed-Signal VLSI Integrated Circuits and Systems; IC Design for Wireless and Wireline Communications; New Radio System Architectures for Next-Generation Wireless Standards; RF/Wireless System-on-Chip(SoC);

Contact Details

  • School of Electrical Sciences
  • +91 674 713 5778
  • vijay@iitbbs.ac.in

Other Profile Link(s)

Education

 Degree Discipline Year School
 Ph.D. Microelectronics and VLSI Design 2011 Indian Institute of Technology Kharagpur
 Post-Doctoral Fellow Analog and Mixed-Signal IC Design 2012 Swiss Federal Institute of Technology, Lausanne (EPFL)
 

Biosketch

 

Teaching

Teaching Interests: Analog Electronics Circuits; Analog CMOS IC Design; Wireless IC Design/RF CMOS IC Design; Wireline IC Design; Digital Integrated Circuits; Introduction to Electronics/Basic Electronics; Low-Power VLSI Design;

 

Recent Publications (International Journals)

1Raviteja Kammari, Jagapathi G, Subrahmanyam Boyapati and Vijaya Sankara Rao Pasupureddi, "Modeling and Design of A Compact Low-Power Folded Cascode OpAmp With High EMI-Immunity", IEEE Transactions on Electromagnetic Compatibility, September 2021(accepted).
2Jagapathi G, Subrahmanyam Boyapati and Vijaya Sankara Rao Pasupureddi; Compact CMOS Miller OpAmp With High EMI-immunity," DOI 10.1109/TEMC.2020.2995103, May, 2020 in IEEE Transactions on Electromagnetic Compatibility.
3Pankaj Venuturuapalli,Prema Kumar Govindaswamy and Vijaya Sankara Rao Pasupureddi, Residue Monitor Enabled Charge-Mode Adaptive Echo-Cancellation for Simultaneous Bidirectional Signaling over On-Chip Interconnects, Microelectronics Journal, May, 2020.
4Prema Kumar Govindaswamy and Vijaya Sankara Rao Pasupureddi, A 2^7-1, 20 Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2V, 65nm CMOS, to Circuits, Systems, and Signal Processing; March, 2020.
5Raviteja Kammari and Vijaya Sankara Rao Pasupureddi , "Charge Controlled Delay Element Enabled Widely Linear Power Efficient MPCG-MDLL in 1.2V, 65nm CMOS", Wiely, International Journal of Circuit Theory and Applications, 19 December 2019 https://doi.org/10.1002/cta.2719
6A. Kale, S. Popuri, M. Koeberle, J. Sturm and Vijaya Sankara Rao Pasupureddi, "A −40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 3, pp. 1166-1179, March 2019.
7A −40 dB EVM 20MHz subsampling multistandard receiver architecture with dynamic carrier detection, bandwidth estimation, and EVM optimization, Ajinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi, Wiely, International Journal of Circuit Theory and Applications, First published: 18 February 2019 https://doi.org/10.1002/cta.2601.
8Ajinkya Kale, Graciele Batistell, Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi, Wolfgang Boesch, Johannes Sturm, “Integration Solutions for Reconfigurable Multi-Standard Wireless Transceivers”, e&i elektrotechnik und Informationstechnik, Springer Wien, 2018.
9Prateek Pendyala and Vijaya Sankara Rao Pasupureddi, “100-Mb/s Enhanced Data Rate MIL-STD-1553B Controller in 65-nm CMOS Technology” IEEE Transactions on Aerospace and Electronic Systems, Page(s): 2917 - 2929, December 2016, DOI: 10.1109/TAES.2016.150564
10Divya Duvvuri, and Vijaya Sankara Rao Pasupureddi, “"Design and Analysis of a Current Mode Integrated CTLE with Charge Mode Adaptation" Volume 53, Pages 81-89, Elsevier Microelectronics Journal.
11Ajinkya Kale, Ramakrishna Thirumuru and Vijaya Sankara Rao Pasupureddi , “Wideband Channelized Sub-sampling Transceiver for Digital RF Memory based Electronic Attack System”, Elsevier Aerospace Science and Technology, Volume 51, April 2016, Pages 34–41, doi:10.1016/j.ast.2016.01.009
12Vijaya Sankara Rao P, Pradip Mandal, "Current-Mode Full-Duplex(CMFD) Signaling for Publications High-Speed Chip-to-Chip Interconnect' Elsevier: Microelectronics Journal, 42(2011)957965.
13Vijaya Sankara Rao P, Nachiket Desai and Pradip Mandal, "A Low Power 5 Gb/s Current-Mode LVDS Output Driver with Active Termination Circuits, Systems and Signal Processing, Springer DOI: 10.1007/s00034-011-9280-2
14Mrigank Sharad, Vijaya Sankara Rao P and Pradip Mandal "Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications", Springer Analog Integrated Circuits and Signal Processing, Volume 68 Issue 3, September 2011, Pages 361-377.
15Vijaya Sankara Rao P, Pradip Mandal, A new current-mode receiver for high-speed electrical/optical link", Elsevier: International Journal of Electronics and Communication (2010), doi:10.1016/j.aeue.2010.01.018.
16Vijaya Sankara Rao P, Pradip Mandal, Active Terminated Transmitter and Receiver Circuits for High-Speed Low-Swing Duobinary Signaling", Wiley: International Journal of Circuit Theory and Applications(2010),DOI: 10.1002/cta.730.
17Vijaya Sankara Rao P, Pradip Mandal and Debashis Banerjee " Active Terminated Current-Mode Pre-emphasis Transmitter for PCI Express Standard" Elsevier: International Journal of Electronics and Communication,10.1016/j.aeue.2010.09.007.
18Vijaya Sankara Rao P, Pradip Mandal, "Current-Mode Analogue Interface for High-Speed Low-Current Differential Signalling", In Taylor & Francis: International Journal of Electronics, Volume 97, Issue 9, Pages 1007 to 1020, 2010.

Conferences (International)

1Prema Kumar Govindaswamy, Nijwm Wary and Vijaya Sankara Rao Pasupureddi, “A Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects”, has been accepted for presentation at the 2022 IEEE International Symposium on Circuits & Systems, to be held in Austin, Texas USA from May 28 through June 1, 2022
2Prema Kumar Govindaswamy, Nijwm Wary and Vijaya Sankara Rao Pasupureddi, “Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects”, has been accepted for presentation at the 2022 IEEE International Symposium on Circuits & Systems, to be held in Austin, Texas USA from May 28 through June 1, 2022.
3Rakesh Rena, Suraj Kumar Verma, Vijaya Sankara Rao Pasupureddi, "A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End", 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea from May 22-28, 2021.
4Prema Kumar Govindaswamy and Vijaya Sankara Rao Pasupureddi; A 2^7-1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65 nm CMOS'IEEE Computer Society Annual Symposium on VLSI GrandResort, Limassol, CYPRUS, July 6-8, 2020
5Pankaj Venuturuapalli,Prema Kumar Govindaswamy and Vijaya Sankara Rao Pasupureddi "An Adaptive Hybrid with Residue Monitor for Full-Duplex On-Chip Interconnects", 2020 IEEE International Symposium on Circuits & Systems, Seville, Spain, May 17-20, 2020
6Raviteja Kammari and Vijaya Sankara Rao Pasupureddi A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-Phase Clock Generation in 1.2V, 65nm CMOS, The 23rd International Symposium on VLSI Design and Test (VDAT-2019)(accepted for oral presentation)
7A. Kale, S. Popuri, M. Koeberle, J. Sturm and V. S. R. Pasupureddi, 0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), August 9, 2018
8Suchendranath Popuri, Vijaya Sankara Rao Pasupureddi and Johannes Sturm, “A Tunable Gain and Tunable Band Active Balun LNA for IEEE 802.11ac WLAN Receivers” European solid state circuits conference 2016, ESSCIRC 2016, held in Lausanne, Switzerland from 12-15 September 2016.
9Pratap Tumkur Renukaswamy, Vijaya Sankara Rao Pasupureddi and Johannes Sturm, “Analysis and Design of Differential Feedback CG LNA Topologies for Low Voltage Multistandard Wireless Receivers”, IEEE Austrochip, October 2016, Villach, Austria.
10Darshan Shetty,, Vijaya Sankara Rao Pasupureddi and Johannes Sturm, “A 2.4 GHz, 1 dB Noise Figure Common-Gate LNA for WLAN Frontend”, IEEE 24th Telecommunications forum TELFOR 2016, Serbia, Belgrade, November 22-23, 2016.
11Divya Duvvuri, and Vijaya Sankara Rao Pasupureddi, An Integrated Current Mode CTLE Receiver Front End with Charge Mode Adaptation, IEEE Computer Society Annual Symposium on VLSI, Pittsburgh, Pennsylvania, U.S.A., July 11-13, 2016
12Divya Duvvuri, and Vijaya Sankara Rao Pasupureddi "A New Hybrid Circuit Topology for Simultaneous Bidirectional Signaling Over on-Chip Interconnects"2016 IEEE Int'l Symposium on Circuits & Systems, to be held in Montreal, Canada from May 22-26, 2016.
13Prateek Pendyala and Vijaya Sankara Rao Pasupureddi, “Backward Compatible Mil-STD-1553B Analog Transceiver Upgrade for 100-Mb/S Data Rate” 20th International Symposium on VLSI Design and Test VDAT-2016, May 24th- May 27th 2016, Guwahati, India.
14Bhuvanan, K. and Vijaya Sankara Rao Pasupureddi “A Low Power Charge Mode Compressive Acquisition of Multichannel EEG Signals”, 2016 IEEE Int'l Symposium on Circuits & Systems, to be held in Montreal, Canada from May 22-26, 2016
15Prateek Pendyala and Vijaya Sankara Rao Pasupureddi "MIl-STD-1553+: Integrated Remote Terminal and Bus Controller at 100-Mb/S Data Rate”, 2015 IEEE Int'l Symposium on Circuits & Systems, Portugal, May 24-27, 2015.-ISCAS 2015
16Prateek Pendyala and Vijaya Sankara Rao Pasupureddi " "RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate," IEEE 16th International Symposium on Quality Electronic Design (ISQED 2015)”. Santa Clara, CA, 2015, pp. 502-506. doi: 10.1109/ISQED.2015.7085476
17Divya Duvvuri, Vijaya Sankara Rao P and Chattopadhyay J “a 100 Mb/s transceiver for Enhanced MIL-STD-1553”, IEEE Asia Pacific Conference on Circuits and Systems, 17-20 November, 2014, Okinawa, Japan.
18Ajinkya Kale and Vijaya Sankara Rao P and Chattopadhyay J “Design and Simulation of Wideband Channelized Transceiver for DRFM Application”, IEEE Asia Pacific Conference on Circuits and Systems, 17-20 November 2014, Okinawa, Japan.
19Somanshu Agarwal and Vijaya Sankara Rao P, “A 5Gb/s Adaptive Continuous-Time Linear Equalizer with Eye-Monitoring” The IEEE 57th International Midwest Symposium on Circuits and Systems, College Station, Texas, USA, August 3-6, 2014.
20R. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti: A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source. IEEE VLSI Design 2014: 575-579.
21Bhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi: A Low Power CMOS Imager Based on Distributed Compressed Sensing. IEEE VLSI Design 2014: 534-538.
22Shoaran Mahsa, mariazel.maqueda, Vijaya Sankara Rao P, Leblebici Yusuf, and Schmid Alexandre "A Low-Power Area-Efficient Compressive Sensing Approach for Multi-Channel Neural Recording ", 2013 IEEE International Symposium on Circuits and Systems, Beijing, China, 19-23 May, 2013.
23Bhuvanan, K. ; Krishna, Abhiram Sai ; Golla, Govardhan ; Vijaya Sankara Rao P, "A Multi-camera Wireless Capsule Endoscopic System", IEEE India Educators' Conference (TIIEC), 2013 Texas Instruments, 65-68, 4-6 April 2013.
24Bhuvanan Kaliannan, Vijaya Sankara Rao P, "Implementation of a Charge Redistribution Based 2-D DCT Architecture for Wireless Capsule Endoscopy ", 26th IEEE International Conference on VLSI Design, 5-10, Jan. 2013, Chennai, India
25Mriagnak Sharad, Vijaya Sankara Rao P and Pradip Mandal, "A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture", 24th IEEE International Conference on VLSI Design, 2-7, Jan. 2011, Chennai, India
26Vijaya Sankara Rao P, Pradip Mandal," Current-Mode Echo Cancellation for Full-Duplex Chip-to-Chip Data Communication", 2010 IEEE Asia Pacific Conference on Circuits and Sys-tems, 6-9 December, Kuala Lumpur, Malaysia
27Vijaya Sankara Rao P, Pradip Mandal "A New Power Efficient Current-Mode 4-PAM Transmitter Interface for Off-Chip Interconnect",2010 IEEE Asia Pacific Conference on Circuits and Systems, 6-9 December, Kuala Lumpur, Malaysia.
28Vijaya Sankara Rao P, Pradip Mandal and Sunil Sachdev, "High-Speed Low-Current Duobi-nary Signaling Over Active Terminated Chip-to-Chip Interconnect", IEEE Annual Symposium on VLSI, May 13-15,Tampa, Florida, USA, 2009.
29Vijaya Sankara Rao P, Pradip Mandal," Self-Termination Scheme for High-Speed Chip-to-Chip Data Communication ", IEEE International Symposium on Signals, Circuits and Sys-tems(ISSCS),July 9-10, Iasi, Romania, 2009
30Vijaya Sankara Rao P, Mrigank Sharad and Pradip Mandal, "High-Speed Transmitter for Fully Differential Current-Mode Polyquaternary Signaling Scheme", IEEE International Midwest Symposium on Circuits and Systems(MWSCAS 2009), August 2-5, Cancn, Mexico, 2009
31Pradip Mandal, Sailesh Pati, Vijaya Sankara Rao P, " Active Terminated Differential Current-Mode Receiver for High-Speed Data Communication", IEEE NEWCAS-TAISA'09, June28-July 01, Toulouse, France, 2009
32T V Kalyan, Madhu Mutyam, Vijaya Sankara Rao P "Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design", 21st International IEEE Conference on VLSI Design Hyderabad, India, 2008.
 

Academic Honors & Awards

  • RESEARCH AND CONSULTANCY PROJECTS ARE LISTED BELOW:
  • Design of Dynamic MAC and PHY SoC for Low Power and Long Range Networks, Ministry of Electronics & Information Technology, Govt. of India-, INR. 42 Lakhs, 2021-2023.
  • European Union, FFG Austria, Project Ideation in collaboration with Infineon Technologies, Austria/Germany, 2016-2020, EUR. 4,20,000 (Rs. 3.38 Crores)
  • In-Band Full-Duplex Signaling with Digitally Assisted Self-Interference Cancellation for the Next Generation (5G) Mobile Networks Research, design and development of self-interference cancellation (SIC) integrated circuits July, 2017 to June, 2019, Funding from UGC, Govt. of India. Rs. 10 Lakhs.
  • Simultaneous Bidirectional Data Link over On-Chip Global MIMO Interconnect Research, design and development of pseudo-random binary sequence (PRBS) generator for simultaneous bidirectional data link over on-chip global MIMO interconnect May, 2017 to April, 2020 Funding from Carinthia University of Applied Sciences, Austria, Rs. 35 Lakhs
  • Design and Development of DRFM and Superbus Systems for Long Range Missiles, Sponsored by Advanced Systems Laboratory, Defense Research and Development Authority , Govt. of India, 2013-2014, 1 year, 49.25 Lakhs Indian Rupees (ends on 24th, September 2014) as Principal Investigator.
  • Virtual Lab on Analog and Mixed Signal VLSI Design, Sponsored by MHRD, Govt. of India, 2011-2014, 3 years, 15 Lakh Indian Rupees.
 

Research Scholar

Record not found. Please check back later.

 

Assistant Professor, Depatment of Electrical Engineering, Indian Institute of Technology Ropar, 2014-15
 

Post-Doctoral Fellow: Microelectronic Systems Laboratory, Swiss Federal Institute of Technology, Lausanne (EPFL), Switzerland, 2012-13

Editorial Board Member, Journal of Low Power Electronics and Applications, MDPI 

Adjunct Associate Professor, Carinthia University of Applied Sciences, Austria, 2017-20

Associate Professor(Senior Lecturer), Carinthia University of Applied Sciences, Austria, 2015-17

Executive Committee Member, IEEE Circuits and Systems Society, IEEE Hyderabad Section

Member, IEEE

Member, IEEE Solid State Circuits Society

Life Member, IETE

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